1. Field of the Invention
The present invention relates to a non-volatile memory device and a method for fabricating the same.
2. Description of the Related Art
The performance of ULSI devices greatly depends on the performance of a gate oxide film, and a basic problem is how to form a highly reliable gate oxide film. The fact that the formation of the gate oxide film is a key process in device manufacture even today is attributable to possible deterioration of the oxide film due to various causes. Specifically, the oxide film is greatly influenced not only by the conditions of its formation but also by the pre- and post-processes as well as its structure. For these reasons, there have been attempts to develop oxide films which are robust against external causes and not easily affected by external influences.
Many current devices use inter-layer insulating films. In addition, various methods have been tried for forming an oxide film as an insulating film, for instance, a CVD (Chemical Vapor Deposition) process for forming BPSG (Boro-Phospho-Silicate Glass) films, PSG films, BSG films, etc. However, these inter-layer insulating films contain, in addition to a high water content, additional impurities such as boron and phosphorus, thus posing a problem that these impurities diffuse even as far as the gate oxide film, leading to a deterioration of reliability. Therefore, a means for preventing such diffusion is necessary.
FIG. 1 shows, in a sectional view, a prior art example of a non-volatile memory device.
The memory device shown in FIG. 1 comprises a multi-layered structure of memory gate electrodes (hereinafter referred to as a "multi-layered gate electrode structure"), which is formed on a p-type silicon substrate 1 by depositing sequentially from a bottom a first gate insulating film 2, a floating gate electrode 3, a second gate insulating film 4, and a control gate electrode 5; a source/drain diffusion layer 6 which is formed in surface regions of the silicon substrate 1 by ion-implantation of an n-type impurity and which is self-aligned with the multi-layered gate electrode structure; an oxidized silicon film 11 formed on the side surfaces of the gate electrode structure; a nitrified silicon film 12 deposited by the CVD process on surfaces inclusive of surfaces of the gate electrode structure and the source/drain diffusion layer 6; and an inter-layer insulating film 10, such as a BPSG film, formed on the nitrified silicon film 12. With the provision of the nitrified silicon film 12, it is possible to prevent the diffusion of the water and such impurities as boron and phosphorus from the inter-layer insulating film 10 into the gate insulating film thereby preventing the device operation from becoming unstable due to trapping of electrons or generation of dangling bonds. In addition, the nitrified silicon film 12 is formed on the surface of the source/drain diffusion layer 6 either directly or with a thin thermally oxidized silicon film being interposed therebetween. By setting the thickness of the thermally oxidized silicon film to be between 0 and 100 nm, it is possible to block the entry of sodium (Na) ions through contact hole 13 (refer to Japanese Patent Application Kokai Publication No. Hei 1-164069).
This prior art semiconductor device has a problem that the memory section is subjected to a very high stress caused by the deposited nitrified silicon film. If the deposition surface is flat and the deposited nitrified silicon film is sufficiently thin, the stress applied to the section on which the deposition is made is not so high. However, with deposition of nitrified silicon film on a portion having a large step, such as on the multi-layered gate electrode structure of a non-volatile memory device, great strain is generated in the covered electrode and the insulating film, leading to an increased leakage in the insulating film and deterioration of the reliability of the device. Further, in the case of depositing a nitrified silicon film on the thermally oxidized silicon film, many inter-atomic mismatches develop at the interface between the thermally oxidized film and the nitrified silicon film so that there is tendency for a leakage current to flow through such an interface. This is a fatal problem in the non-volatile memory device.